A year ago, I added a softcore CPU to SNESTang, to make FPGA gaming cores easier to use. Over the past months, this allowed me to implement features like an improved menu system and core switching. While the softcore served its purpose, its limitations—slow performance, inability to handle complex peripherals like USB, and FPGA resource consumption—became apparent. Now is again the time to introduce some changes. After extensive collaboration with the Sipeed team, we’ve finally found a way to tap the Tang boards’ onboard MCU (a Bouffalo BL616 chip) to address these challenges. The result is TangCore 0.6, along with all four gaming cores. In this post, I’ll discuss integrating the MCU with the Tang gaming cores.

I’ve recently found myself frequently using the “ChatGPT to PDF” Chrome extension to convert ChatGPT conversations into PDF documents. The Deep Research discussions in particular contain valuable info worth preserving in ebook format. However they lack proper title pages. So here’s a quick Python script to add a simple title page to PDF documents.

Universal Asynchronous Receiver-Transmitter (UART) modules are basic components in embedded systems, enabling serial communication between devices. While there are many free implementations available online, a new challenge arose during my work on the independent software stack for the Tang Console: non-integer clock multiples. This issue surfaced when FPGA cores running on clocks of different frequencies need to communicate with an MCU via UART. Unlike SPI, where the master dictates the clock, UART demands both sides to adhere to a pre-agreed-upon baud rate (1Mbps in my case). Traditional integer clock dividers in this case yield imprecise baud rates and communication errors. In this post, I’ll explore a nice solution using a fractional clock divider technique.

Today we discuss Sega Genesis (or Mega Drive). The 16-bit game consoles held a special place in game history. After the 8-bit machines became extremely popular in the mid-1980s, companies had more resources to pour into R&D of the next generation, leading to more sophisticated designs. And the users truly desired “arcade-level performance”, hence the “Blast Processing” marketing by Sega. These machines were well-received and significantly pushed the industry forward. Although companies like NEC and SNK entered the home console market during this period, the main rivalry was between two companies, Nintendo and Sega. SNESTang has been available for some time now. It is about time I bring the other major 16-bit machine, Sega Genesis or Mega Drive, to the Tang boards. MDTang 0.1 is a port of Genesis-MiSTer to Tang Mega 138K/138K Pro. In the future, it will also support TangConsole 60K when it is released.

GBATang has been improving pretty quickly since its release and just reached version 0.4. More games are running. Graphics rendering has improved a lot. And sound bugs were fixed. Continuing part one, let us discuss the components that were not covered in the first post.

Here are a few tips and tricks for using the Gowin EDA IDE and Tang FPGA boards, such as Tang Nano 20K, Tang Primer 25K and Tang Mega 138K. These are small things that I wish I knew when picking up the Tang boards. Gowin is a relatively small FPGA vendor and documentation is not that complete. So I hope this is helpful for the community. If you are coming from Xilinx or Intel FPGAs, you may also find these useful for quickly getting started.

Version 0.1 of GBATang is just released. It is the first FPGA core for a 32-bit console available for Tang FPGA boards (Tang Mega 138K and the upcoming 60K). The journey is an interesting one for me. This first blog post discusses the experience of porting and building this core, its overall technical design and in more details, the CPU part.

In part 1, we discussed why we need a softcore for SNESTang, and how it can use SDRAM in a way that does not disrupt the gaming core. Now we need to provide a firmware program to to make the softcore useful, like displaying a menu. In this part, let’s explore the building and loading of the RISC-V firmware to get the soft core to do useful work.

In the recently released SNESTang 0.3, a softcore-based I/O system is added to enhance the menu system and file system support. Let us explore how this works. Part one of the article discusses why the soft core is necessary, choice of CPU to use and how it works with the SDRAM.

This documents the design of SNESTang 0.3 for my own reference and others who want to read the code. It also aims to be helpful to people porting other cores to Tang FPGAs.